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Node / ReticulumProjects / RNode_Firmware.git / files / sx126x.cpp

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sx126x.cpp bc97e513e8192eb00ba5d7577adf3d20a3a653e6 (bc97e513) Text, 23.60 KB

T8b949e// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.

T8b949e// Licensed under the MIT license.

Tff7b72#Tff7b72include T8b949e"Boards.h"

Tff7b72#Tff7b72if MODEM == SX1262

Tff7b72#Tff7b72include T8b949e"sx126x.h"

Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32

Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32 and !defined(CONFIG_IDF_TARGET_ESP32S3)

Tff7b72#Tff7b72include T8b949e"soc/rtc_wdt.h"

Tff7b72#Tff7b72endif

Tff7b72#Tff7b72define ISR_VECT IRAM_ATTR

Tff7b72#Tff7b72else

Tff7b72#Tff7b72define ISR_VECT

Tff7b72#Tff7b72endif

Tff7b72#Tff7b72define OP_RF_FREQ_6X 0x86

Tff7b72#Tff7b72define OP_SLEEP_6X 0x84

Tff7b72#Tff7b72define OP_STANDBY_6X 0x80

Tff7b72#Tff7b72define OP_TX_6X 0x83

Tff7b72#Tff7b72define OP_RX_6X 0x82

Tff7b72#Tff7b72define OP_PA_CONFIG_6X 0x95

Tff7b72#Tff7b72define OP_SET_IRQ_FLAGS_6X 0x08 T8b949e// Also provides info such as

T8b949e// preamble detection, etc for

T8b949e// knowing when it's safe to switch

T8b949e// antenna modes

Tff7b72#Tff7b72define OP_CLEAR_IRQ_STATUS_6X 0x02

Tff7b72#Tff7b72define OP_GET_IRQ_STATUS_6X 0x12

Tff7b72#Tff7b72define OP_RX_BUFFER_STATUS_6X 0x13

Tff7b72#Tff7b72define OP_PACKET_STATUS_6X 0x14 T8b949e// Get snr & rssi of last packet

Tff7b72#Tff7b72define OP_CURRENT_RSSI_6X 0x15

Tff7b72#Tff7b72define OP_MODULATION_PARAMS_6X 0x8B T8b949e// BW, SF, CR, etc.

Tff7b72#Tff7b72define OP_PACKET_PARAMS_6X 0x8C T8b949e// CRC, preamble, payload length, etc.

Tff7b72#Tff7b72define OP_STATUS_6X 0xC0

Tff7b72#Tff7b72define OP_TX_PARAMS_6X 0x8E T8b949e// Set dbm, etc

Tff7b72#Tff7b72define OP_PACKET_TYPE_6X 0x8A

Tff7b72#Tff7b72define OP_BUFFER_BASE_ADDR_6X 0x8F

Tff7b72#Tff7b72define OP_READ_REGISTER_6X 0x1D

Tff7b72#Tff7b72define OP_WRITE_REGISTER_6X 0x0D

Tff7b72#Tff7b72define OP_DIO3_TCXO_CTRL_6X 0x97

Tff7b72#Tff7b72define OP_DIO2_RF_CTRL_6X 0x9D

Tff7b72#Tff7b72define OP_CAD_PARAMS 0x88

Tff7b72#Tff7b72define OP_CALIBRATE_6X 0x89

Tff7b72#Tff7b72define OP_RX_TX_FALLBACK_MODE_6X 0x93

Tff7b72#Tff7b72define OP_REGULATOR_MODE_6X 0x96

Tff7b72#Tff7b72define OP_CALIBRATE_IMAGE_6X 0x98

Tff7b72#Tff7b72define MASK_CALIBRATE_ALL 0x7f

Tff7b72#Tff7b72define IRQ_TX_DONE_MASK_6X 0x01

Tff7b72#Tff7b72define IRQ_RX_DONE_MASK_6X 0x02

Tff7b72#Tff7b72define IRQ_HEADER_DET_MASK_6X 0x10

Tff7b72#Tff7b72define IRQ_PREAMBLE_DET_MASK_6X 0x04

Tff7b72#Tff7b72define IRQ_PAYLOAD_CRC_ERROR_MASK_6X 0x40

Tff7b72#Tff7b72define IRQ_ALL_MASK_6X 0b0100001111111111

Tff7b72#Tff7b72define MODE_LONG_RANGE_MODE_6X 0x01

Tff7b72#Tff7b72define OP_FIFO_WRITE_6X 0x0E

Tff7b72#Tff7b72define OP_FIFO_READ_6X 0x1E

Tff7b72#Tff7b72define REG_OCP_6X 0x08E7

Tff7b72#Tff7b72define REG_LNA_6X 0x08AC T8b949e// No agc in sx1262

Tff7b72#Tff7b72define REG_SYNC_WORD_MSB_6X 0x0740

Tff7b72#Tff7b72define REG_SYNC_WORD_LSB_6X 0x0741

Tff7b72#Tff7b72define REG_PAYLOAD_LENGTH_6X 0x0702 T8b949e// https://github.com/beegee-tokyo/SX126x-Arduino/blob/master/src/radio/sx126x/sx126x.h#L98

Tff7b72#Tff7b72define REG_RANDOM_GEN_6X 0x0819

Tff7b72#Tff7b72define MODE_TCXO_3_3V_6X 0x07

Tff7b72#Tff7b72define MODE_TCXO_3_0V_6X 0x06

Tff7b72#Tff7b72define MODE_TCXO_2_7V_6X 0x06

Tff7b72#Tff7b72define MODE_TCXO_2_4V_6X 0x06

Tff7b72#Tff7b72define MODE_TCXO_2_2V_6X 0x03

Tff7b72#Tff7b72define MODE_TCXO_1_8V_6X 0x02

Tff7b72#Tff7b72define MODE_TCXO_1_7V_6X 0x01

Tff7b72#Tff7b72define MODE_TCXO_1_6V_6X 0x00

Tff7b72#Tff7b72define MODE_STDBY_RC_6X 0x00

Tff7b72#Tff7b72define MODE_STDBY_XOSC_6X 0x01

Tff7b72#Tff7b72define MODE_FALLBACK_STDBY_RC_6X 0x20

Tff7b72#Tff7b72define MODE_IMPLICIT_HEADER 0x01

Tff7b72#Tff7b72define MODE_EXPLICIT_HEADER 0x00

Tff7b72#Tff7b72define SYNC_WORD_6X 0x1424

Tff7b72#Tff7b72define XTAL_FREQ_6X (double)32000000

Tff7b72#Tff7b72define FREQ_DIV_6X (double)pow(2.0, 25.0)

Tff7b72#Tff7b72define FREQ_STEP_6X (double)(XTAL_FREQ_6X Tff7b72/Tff7b72 FREQ_DIV_6X)

Tff7b72#Tff7b72if BOARD_MODEL == BOARD_TECHO

Te6edf3SPIClass Te6edf3spim3 Tff7b72= Te6edf3SPIClassTb4b4b4(Te6edf3NRF_SPIM3Tb4b4b4, Te6edf3pin_misoTb4b4b4, Te6edf3pin_sclkTb4b4b4, Te6edf3pin_mosiTb4b4b4) Tb4b4b4;

Tff7b72#Tff7b72define SPI spim3

Tff7b72#Tff7b72elif defined(NRF52840_XXAA)

Tff7b72extern Te6edf3SPIClass Te6edf3spiModemTb4b4b4;

Tff7b72#Tff7b72define SPI spiModem

Tff7b72#Tff7b72endif

Tff7b72extern Te6edf3SPIClass Te6edf3SPITb4b4b4;

Tff7b72#Tff7b72define MAX_PKT_LENGTH 255

Te6edf3sx126xTff7b72:Tff7b72:Te6edf3sx126xTb4b4b4(Tb4b4b4) Tff7b72:

Te6edf3_spiSettingsTb4b4b4(T79c0ff16E6Tb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4,

Te6edf3_ssTb4b4b4(Te6edf3LORA_DEFAULT_SS_PINTb4b4b4)Tb4b4b4, Te6edf3_resetTb4b4b4(Te6edf3LORA_DEFAULT_RESET_PINTb4b4b4)Tb4b4b4, Te6edf3_dio0Tb4b4b4(Te6edf3LORA_DEFAULT_DIO0_PINTb4b4b4)Tb4b4b4, Te6edf3_busyTb4b4b4(Te6edf3LORA_DEFAULT_BUSY_PINTb4b4b4)Tb4b4b4, Te6edf3_rxenTb4b4b4(Te6edf3LORA_DEFAULT_RXEN_PINTb4b4b4)Tb4b4b4,

Te6edf3_frequencyTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,

Te6edf3_txpTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,

Te6edf3_sfTb4b4b4(T79c0ff0x07Tb4b4b4)Tb4b4b4,

Te6edf3_bwTb4b4b4(T79c0ff0x04Tb4b4b4)Tb4b4b4,

Te6edf3_crTb4b4b4(T79c0ff0x01Tb4b4b4)Tb4b4b4,

Te6edf3_ldroTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4,

Te6edf3_packetIndexTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,

Te6edf3_preambleLengthTb4b4b4(T79c0ff18Tb4b4b4)Tb4b4b4,

Te6edf3_implicitHeaderModeTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,

Te6edf3_payloadLengthTb4b4b4(T79c0ff255Tb4b4b4)Tb4b4b4,

Te6edf3_crcModeTb4b4b4(T79c0ff1Tb4b4b4)Tb4b4b4,

Te6edf3_fifo_tx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,

Te6edf3_fifo_rx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,

Te6edf3_packetTb4b4b4(Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4)Tb4b4b4,

Te6edf3_preinit_doneTb4b4b4(Tffa657falseTb4b4b4)Tb4b4b4,

Te6edf3_onReceiveTb4b4b4(Tffa657NULLTb4b4b4)

Tb4b4b4{ Te6edf3setTimeoutTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657bool Te6edf3sx126xTff7b72:Tff7b72:Te6edf3preInitTb4b4b4(Tb4b4b4) Tb4b4b4{

T8b949e// delay(300);

T8b949e//LoRa->reset();

T8b949e// reset();

T8b949e// delay(100);

Te6edf3pinModeTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72if BOARD_MODEL == BOARD_T3S3 || BOARD_MODEL == BOARD_HELTEC32_V3 || BOARD_MODEL == BOARD_TDECK

Te6edf3SPITb4b4b4.Te6edf3beginTb4b4b4(Te6edf3pin_sclkTb4b4b4, Te6edf3pin_misoTb4b4b4, Te6edf3pin_mosiTb4b4b4, Te6edf3pin_csTb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TECHO T8b949e// || BOARD_MODEL == BOARD_SEEED_XIAO_ESP32S3

Te6edf3SPITb4b4b4.Te6edf3setPinsTb4b4b4(Te6edf3pin_misoTb4b4b4, Te6edf3pin_sclkTb4b4b4, Te6edf3pin_mosiTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72else

Te6edf3SPITb4b4b4.Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72endif

T8b949e// Check version (retry for up to 2 seconds)

T8b949e// TODO: Actually read version registers, not syncwords

Tffa657long Te6edf3start Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;

Tffa657uint8_t Te6edf3syncmsbTb4b4b4;

Tffa657uint8_t Te6edf3synclsbTb4b4b4;

Tff7b72while Tb4b4b4(Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72- Te6edf3startTb4b4b4) Tff7b72< T79c0ff2000Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Te6edf3startTb4b4b4)Tb4b4b4) Tb4b4b4{

Te6edf3syncmsb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_MSB_6XTb4b4b4)Tb4b4b4;

Te6edf3synclsb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_LSB_6XTb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4( Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72=Tff7b72= T79c0ff0x1424 Tff7b72|Tff7b72| Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72=Tff7b72= T79c0ff0x4434Tb4b4b4) Tb4b4b4{

Tff7b72breakTb4b4b4;

Tb4b4b4}

Te6edf3delayTb4b4b4(T79c0ff100Tb4b4b4)Tb4b4b4;

Te6edf3SerialTb4b4b4.Te6edf3printlnTb4b4b4( Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tff7b72if Tb4b4b4( Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72!Tff7b72= T79c0ff0x1424 Tff7b72&Tff7b72& Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72!Tff7b72= T79c0ff0x4434Tb4b4b4) Tb4b4b4{

Tff7b72return Tffa657falseTb4b4b4;

Tb4b4b4}

Te6edf3_preinit_done Tff7b72= Tffa657trueTb4b4b4;

Tff7b72return Tffa657trueTb4b4b4;

Tb4b4b4}

Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3readRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4) Tb4b4b4{

Tff7b72return Te6edf3singleTransferTb4b4b4(Te6edf3OP_READ_REGISTER_6XTb4b4b4, Te6edf3addressTb4b4b4, T79c0ff0x00Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4) Tb4b4b4{

Te6edf3singleTransferTb4b4b4(Te6edf3OP_WRITE_REGISTER_6XTb4b4b4, Te6edf3addressTb4b4b4, Te6edf3valueTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3singleTransferTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4) Tb4b4b4{

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Tffa657uint8_t Te6edf3responseTb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Tb4b4b4(Te6edf3address Tff7b72& T79c0ff0xFF00Tb4b4b4) Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3address Tff7b72& T79c0ff0x00FFTb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3opcode Tff7b72=Tff7b72= Te6edf3OP_READ_REGISTER_6XTb4b4b4) Tb4b4b4{ Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3response Tff7b72= Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3valueTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Tff7b72return Te6edf3responseTb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3rxAntEnableTb4b4b4(Tb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4; Tb4b4b4}

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3loraModeTb4b4b4(Tb4b4b4) Tb4b4b4{

T8b949e// Enable lora mode on the SX1262 chip

Tffa657uint8_t Te6edf3mode Tff7b72= Te6edf3MODE_LONG_RANGE_MODE_6XTb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_TYPE_6XTb4b4b4, Tff7b72&Te6edf3modeTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3waitOnBusyTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657unsigned Tffa657long Te6edf3time Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{

Tff7b72while Tb4b4b4(Te6edf3digitalReadTb4b4b4(Te6edf3_busyTb4b4b4) Tff7b72=Tff7b72= Te6edf3HIGHTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Tb4b4b4(Te6edf3time Tff7b72+ T79c0ff100Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3executeOpcodeTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4) Tb4b4b4{

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;

Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3executeOpcodeReadTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4) Tb4b4b4{

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;

Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeBufferTb4b4b4(Tff7b72const Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_WRITE_6XTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3_fifo_tx_addr_ptrTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3readBufferTb4b4b4(Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_READ_6XTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3_fifo_rx_addr_ptrTb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;

Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setModulationParamsTb4b4b4(Tffa657uint8_t Te6edf3sfTb4b4b4, Tffa657uint8_t Te6edf3bwTb4b4b4, Tffa657uint8_t Te6edf3crTb4b4b4, Tffa657int Te6edf3ldroTb4b4b4) Tb4b4b4{

T8b949e// Because there is no access to these registers on the sx1262, we have

T8b949e// to set all these parameters at once or not at all.

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4]Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3sfTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3bwTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3crTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3ldroTb4b4b4; T8b949e// Low data rate toggle

Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// Unused params in LoRa mode

Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_MODULATION_PARAMS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff8Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setPacketParamsTb4b4b4(Tffa657long Te6edf3preamble_symbolsTb4b4b4, Tffa657uint8_t Te6edf3headermodeTb4b4b4, Tffa657uint8_t Te6edf3payload_lengthTb4b4b4, Tffa657uint8_t Te6edf3crcTb4b4b4) Tb4b4b4{

T8b949e// Because there is no access to these registers on the sx1262, we have

T8b949e// to set all these parameters at once or not at all.

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff9Tb4b4b4]Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tffa657uint8_tTb4b4b4(Tb4b4b4(Te6edf3preamble_symbols Tff7b72& T79c0ff0xFF00Tb4b4b4) Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Tffa657uint8_tTb4b4b4(Tb4b4b4(Te6edf3preamble_symbols Tff7b72& T79c0ff0x00FFTb4b4b4)Tb4b4b4)Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3headermodeTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3payload_lengthTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Te6edf3crcTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// standard IQ setting (no inversion)

Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// unused params

Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_PARAMS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff9Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3resetTb4b4b4(Tffa657voidTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3_reset Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{

Te6edf3pinModeTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;

Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;

Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;

Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3calibrateTb4b4b4(Tffa657voidTb4b4b4) Tb4b4b4{

T8b949e// Put in STDBY_RC mode before calibration

Tffa657uint8_t Te6edf3mode_byte Tff7b72= Te6edf3MODE_STDBY_RC_6XTb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_STANDBY_6XTb4b4b4, Tff7b72&Te6edf3mode_byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

T8b949e// Calibrate RC64k, RC13M, PLL, ADC and image

Tffa657uint8_t Te6edf3calibrate Tff7b72= Te6edf3MASK_CALIBRATE_ALLTb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CALIBRATE_6XTb4b4b4, Tff7b72&Te6edf3calibrateTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

Te6edf3delayTb4b4b4(T79c0ff5Tb4b4b4)Tb4b4b4;

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3calibrate_imageTb4b4b4(Tffa657long Te6edf3frequencyTb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3image_freqTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff430E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff440E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x6BTb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x6FTb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff470E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff510E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x75Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x81Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff779E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff787E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xC1Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xC5Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff863E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff870E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xD7Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xDBTb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff902E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff928E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xE1Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE9Tb4b4b4; Tb4b4b4} T8b949e// TODO: Allow higher freq calibration

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CALIBRATE_IMAGE_6XTb4b4b4, Te6edf3image_freqTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3beginTb4b4b4(Tffa657long Te6edf3frequencyTb4b4b4) Tb4b4b4{

Te6edf3resetTb4b4b4(Tb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_busyTb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4; Tb4b4b4}

Tff7b72if Tb4b4b4(Tff7b72!Te6edf3_preinit_doneTb4b4b4) Tb4b4b4{ Tff7b72if Tb4b4b4(Tff7b72!Te6edf3preInitTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return Tffa657falseTb4b4b4; Tb4b4b4} Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3calibrateTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3calibrate_imageTb4b4b4(Te6edf3frequencyTb4b4b4)Tb4b4b4;

Te6edf3enableTCXOTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3loraModeTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;

T8b949e// Set sync word

Te6edf3setSyncWordTb4b4b4(Te6edf3SYNC_WORD_6XTb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72if DIO2_AS_RF_SWITCH

T8b949e// enable dio2 rf switch

Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x01Tb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_DIO2_RF_CTRL_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72endif

Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3setFrequencyTb4b4b4(Te6edf3frequencyTb4b4b4)Tb4b4b4;

Te6edf3setTxPowerTb4b4b4(T79c0ff2Tb4b4b4)Tb4b4b4;

Te6edf3enableCrcTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3writeRegisterTb4b4b4(Te6edf3REG_LNA_6XTb4b4b4, T79c0ff0x96Tb4b4b4)Tb4b4b4; T8b949e// Set LNA boost

Tffa657uint8_t Te6edf3basebufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; T8b949e// Set base addresses

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_BUFFER_BASE_ADDR_6XTb4b4b4, Te6edf3basebufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;

Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;

Tff7b72return T79c0ff1Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3endTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3sleepTb4b4b4(Tb4b4b4)Tb4b4b4; Te6edf3SPITb4b4b4.Te6edf3endTb4b4b4(Tb4b4b4)Tb4b4b4; Te6edf3_preinit_done Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}

Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3beginPacketTb4b4b4(Tffa657int Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{

Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{ Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tff7b72else Tb4b4b4{ Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3_payloadLength Tff7b72= T79c0ff0Tb4b4b4;

Te6edf3_fifo_tx_addr_ptr Tff7b72= T79c0ff0Tb4b4b4;

Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;

Tff7b72return T79c0ff1Tb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3endPacketTb4b4b4(Tb4b4b4) Tb4b4b4{

Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;

Tffa657uint8_t Te6edf3timeoutTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; T8b949e// Put in single TX mode

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_6XTb4b4b4, Te6edf3timeoutTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

T8b949e// Wait for TX done

Tffa657bool Te6edf3timed_out Tff7b72= Tffa657falseTb4b4b4;

Tffa657uint32_t Te6edf3w_timeout Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tff7b72+Te6edf3LORA_MODEM_TIMEOUT_MSTb4b4b4;

Tff7b72while Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72< Te6edf3w_timeoutTb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_TX_DONE_MASK_6XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4)Tb4b4b4) Tb4b4b4{

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Te6edf3yieldTb4b4b4(Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tff7b72if Tb4b4b4(Tff7b72!Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72< Te6edf3w_timeoutTb4b4b4)Tb4b4b4) Tb4b4b4{ Te6edf3timed_out Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}

T8b949e// Clear IRQs

Tffa657uint8_t Te6edf3maskTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;

Te6edf3maskTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3maskTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3IRQ_TX_DONE_MASK_6XTb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_6XTb4b4b4, Te6edf3maskTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3timed_outTb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff0Tb4b4b4; Tb4b4b4} Tff7b72else Tb4b4b4{ Tff7b72return T79c0ff1Tb4b4b4; Tb4b4b4}

Tb4b4b4}

Tffa657unsigned Tffa657long Te6edf3preamble_detected_at Tff7b72= T79c0ff0Tb4b4b4;

Tff7b72extern Tffa657long Te6edf3lora_preamble_time_msTb4b4b4;

Tff7b72extern Tffa657long Te6edf3lora_header_time_msTb4b4b4;

Tffa657bool Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4;

Tffa657bool Td2a8ffsx126x::dcdTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tffa657uint32_t Te6edf3now Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;

Tffa657bool Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4;

Tffa657bool Te6edf3carrier_detected Tff7b72= Tffa657falseTb4b4b4;

Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_HEADER_DET_MASK_6XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657trueTb4b4b4; Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}

Tff7b72else Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}

Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_PREAMBLE_DET_MASK_6XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{

Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3preamble_detected_at Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3preamble_detected_at Tff7b72= Te6edf3nowTb4b4b4; Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3now Tff7b72- Te6edf3preamble_detected_at Tff7b72> Te6edf3lora_preamble_time_ms Tff7b72+ Te6edf3lora_header_time_msTb4b4b4) Tb4b4b4{

Te6edf3preamble_detected_at Tff7b72= T79c0ff0Tb4b4b4;

Tff7b72if Tb4b4b4(Tff7b72!Te6edf3header_detectedTb4b4b4) Tb4b4b4{ Te6edf3false_preamble_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}

Tffa657uint8_t Te6edf3clearbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3clearbufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3IRQ_PREAMBLE_DET_MASK_6XTb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_6XTb4b4b4, Te6edf3clearbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tb4b4b4}

T8b949e// TODO: Maybe there's a way of unlatching the RSSI

T8b949e// status without re-activating receive mode?

Tff7b72if Tb4b4b4(Te6edf3false_preamble_detectedTb4b4b4) Tb4b4b4{ Te6edf3sx126x_modemTb4b4b4.Te6edf3receiveTb4b4b4(Tb4b4b4)Tb4b4b4; Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}

Tff7b72return Te6edf3carrier_detectedTb4b4b4;

Tb4b4b4}

Tffa657uint8_t Td2a8ffsx126x::currentRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

Tff7b72return Te6edf3byteTb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3ISR_VECT Td2a8ffsx126x::currentRssiTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

Tffa657int Te6edf3rssi Tff7b72= Tff7b72-Tb4b4b4(Tffa657intTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4) Tff7b72/ T79c0ff2Tb4b4b4;

Tff7b72return Te6edf3rssiTb4b4b4;

Tb4b4b4}

Tffa657uint8_t Td2a8ffsx126x::packetRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tff7b72return Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3ISR_VECT Td2a8ffsx126x::packetRssiTb4b4b4(Tb4b4b4) Tb4b4b4{

T8b949e// TODO: May need more calculations here

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tffa657int Te6edf3pkt_rssi Tff7b72= Tff7b72-Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72/ T79c0ff2Tb4b4b4;

Tff7b72return Te6edf3pkt_rssiTb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3ISR_VECT Td2a8ffsx126x::packetRssiTb4b4b4(Tffa657uint8_t Te6edf3pkt_snr_rawTb4b4b4) Tb4b4b4{

T8b949e// TODO: May need more calculations here

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tffa657int Te6edf3pkt_rssi Tff7b72= Tff7b72-Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72/ T79c0ff2Tb4b4b4;

Tff7b72return Te6edf3pkt_rssiTb4b4b4;

Tb4b4b4}

Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetSnrRawTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tff7b72return Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;

Tb4b4b4}

Tffa657float Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetSnrTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tff7b72return Tffa657floatTb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4) Tff7b72* T79c0ff0.25Tb4b4b4;

Tb4b4b4}

Tffa657long Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetFrequencyErrorTb4b4b4(Tb4b4b4) Tb4b4b4{

T8b949e// TODO: Implement this, no idea how to check it on the sx1262

Tff7b72const Tffa657float Te6edf3fError Tff7b72= T79c0ff0.0Tb4b4b4;

Tff7b72return Tff7b72static_castTff7b72<Tffa657longTff7b72>Tb4b4b4(Te6edf3fErrorTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657size_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tffa657uint8_t Te6edf3byteTb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3writeTb4b4b4(Tff7b72&Te6edf3byteTb4b4b4, Tff7b72sizeofTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657size_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tff7b72const Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4) Tff7b72> Te6edf3MAX_PKT_LENGTHTb4b4b4) Tb4b4b4{ Te6edf3size Tff7b72= Te6edf3MAX_PKT_LENGTH Tff7b72- Te6edf3_payloadLengthTb4b4b4; Tb4b4b4}

Te6edf3writeBufferTb4b4b4(Te6edf3bufferTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;

Te6edf3_payloadLength Tff7b72= Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4;

Tff7b72return Te6edf3sizeTb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3availableTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tff7b72return Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72- Te6edf3_packetIndexTb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3readTb4b4b4(Tb4b4b4)Tb4b4b4{

Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3_packetIndex Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tffa657int Te6edf3size Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;

Te6edf3_fifo_rx_addr_ptr Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;

Te6edf3readBufferTb4b4b4(Te6edf3_packetTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657uint8_t Te6edf3byte Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;

Te6edf3_packetIndexTff7b72+Tff7b72+Tb4b4b4;

Tff7b72return Te6edf3byteTb4b4b4;

Tb4b4b4}

Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3peekTb4b4b4(Tb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3_packetIndex Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tffa657int Te6edf3size Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;

Te6edf3_fifo_rx_addr_ptr Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;

Te6edf3readBufferTb4b4b4(Te6edf3_packetTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657uint8_t Te6edf3b Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;

Tff7b72return Te6edf3bTb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3flushTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3onReceiveTb4b4b4(Tffa657voidTb4b4b4(Tff7b72*Te6edf3callbackTb4b4b4)Tb4b4b4(Tffa657intTb4b4b4)Tb4b4b4)Tb4b4b4{

Te6edf3_onReceive Tff7b72= Te6edf3callbackTb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3callbackTb4b4b4) Tb4b4b4{

Te6edf3pinModeTb4b4b4(Te6edf3_dio0Tb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4;

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4]Tb4b4b4; T8b949e// Set preamble and header detection irqs, plus dio0 mask

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4; T8b949e// Set irq masks, enable all

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// Set dio0 masks

Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3IRQ_RX_DONE_MASK_6XTb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// Set dio1 masks

Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// Set dio2 masks

Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SET_IRQ_FLAGS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff8Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT

Te6edf3SPITb4b4b4.Te6edf3usingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72endif

Te6edf3attachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4, Te6edf3sx126xTff7b72:Tff7b72:Te6edf3onDio0RiseTb4b4b4, Te6edf3RISINGTb4b4b4)Tb4b4b4;

Tb4b4b4} Tff7b72else Tb4b4b4{

Te6edf3detachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT

Te6edf3SPITb4b4b4.Te6edf3notUsingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72endif

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3receiveTb4b4b4(Tffa657int Te6edf3sizeTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff0Tb4b4b4) Tb4b4b4{

Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3_payloadLength Tff7b72= Te6edf3sizeTb4b4b4;

Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;

Tb4b4b4} Tff7b72else Tb4b4b4{ Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657uint8_t Te6edf3modeTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0xFFTb4b4b4, T79c0ff0xFFTb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4; T8b949e// Continuous mode

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RX_6XTb4b4b4, Te6edf3modeTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3standbyTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3byte Tff7b72= Te6edf3MODE_STDBY_XOSC_6XTb4b4b4; T8b949e// STDBY_XOSC

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_STANDBY_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3sleepTb4b4b4(Tb4b4b4) Tb4b4b4{ Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x00Tb4b4b4; Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SLEEP_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3enableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{

Tff7b72#Tff7b72if HAS_TCXO

Tff7b72#Tff7b72if BOARD_MODEL == BOARD_RAK4631 || BOARD_MODEL == BOARD_HELTEC32_V3 || BOARD_MODEL == BOARD_SEEED_XIAO_ESP32S3

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_3_3V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TBEAM

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TDECK

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TBEAM_S_V1

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_T3S3

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_HELTEC_T114

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TECHO

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;

Tff7b72#Tff7b72endif

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_DIO3_TCXO_CTRL_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff4Tb4b4b4)Tb4b4b4;

Tff7b72#Tff7b72endif

Tb4b4b4}

T8b949e// TODO: Once enabled, SX1262 needs a complete reset to disable TCXO

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3disableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setTxPowerTb4b4b4(Tffa657int Te6edf3levelTb4b4b4, Tffa657int Te6edf3outputPinTb4b4b4) Tb4b4b4{

T8b949e// Currently no low power mode for SX1262 implemented, assuming PA boost

T8b949e// WORKAROUND - Better Resistance of the SX1262 Tx to Antenna Mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2

T8b949e// RegTxClampConfig = @address 0x08D8

Te6edf3writeRegisterTb4b4b4(T79c0ff0x08D8Tb4b4b4, Te6edf3readRegisterTb4b4b4(T79c0ff0x08D8Tb4b4b4) Tff7b72| Tb4b4b4(T79c0ff0x0F Tff7b72<Tff7b72< T79c0ff1Tb4b4b4)Tb4b4b4)Tb4b4b4;

Tffa657uint8_t Te6edf3pa_bufTb4b4b4[T79c0ff4Tb4b4b4]Tb4b4b4;

Te6edf3pa_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x04Tb4b4b4; T8b949e// PADutyCycle needs to be 0x04 to achieve 22dBm output, but can be lowered for better efficiency at lower outputs

Te6edf3pa_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x07Tb4b4b4; T8b949e// HPMax at 0x07 is maximum supported for SX1262

Te6edf3pa_bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// DeviceSel 0x00 for SX1262 (0x01 for SX1261)

Te6edf3pa_bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= T79c0ff0x01Tb4b4b4; T8b949e// PALut always 0x01 (reserved according to datasheet)

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PA_CONFIG_6XTb4b4b4, Te6edf3pa_bufTb4b4b4, T79c0ff4Tb4b4b4)Tb4b4b4; T8b949e// set pa_config for high power

Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff22Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff22Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff-9Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff-9Tb4b4b4; Tb4b4b4}

Te6edf3writeRegisterTb4b4b4(Te6edf3REG_OCP_6XTb4b4b4, Te6edf3OCP_TUNEDTb4b4b4)Tb4b4b4; T8b949e// Use board-specific tuned OCP

Tffa657uint8_t Te6edf3tx_bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;

Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3levelTb4b4b4;

Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x02Tb4b4b4; T8b949e// PA ramping time - 40 microseconds

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_PARAMS_6XTb4b4b4, Te6edf3tx_bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;

Tb4b4b4}

Tffa657uint8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getTxPowerTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3_txpTb4b4b4; Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setFrequencyTb4b4b4(Tffa657long Te6edf3frequencyTb4b4b4) Tb4b4b4{

Te6edf3_frequency Tff7b72= Te6edf3frequencyTb4b4b4;

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4]Tb4b4b4;

Tffa657uint32_t Te6edf3freq Tff7b72= Tb4b4b4(Tffa657uint32_tTb4b4b4)Tb4b4b4(Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3frequency Tff7b72/ Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3FREQ_STEP_6XTb4b4b4)Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff24Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff16Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff8Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4(Te6edf3freq Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RF_FREQ_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff4Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657uint32_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getFrequencyTb4b4b4(Tb4b4b4) Tb4b4b4{

T8b949e// We can't read the frequency on the sx1262 / 80

Tffa657uint32_t Te6edf3frequency Tff7b72= Te6edf3_frequencyTb4b4b4;

Tff7b72return Te6edf3frequencyTb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setSpreadingFactorTb4b4b4(Tffa657int Te6edf3sfTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{ Te6edf3sf Tff7b72= T79c0ff5Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72> T79c0ff12Tb4b4b4) Tb4b4b4{ Te6edf3sf Tff7b72= T79c0ff12Tb4b4b4; Tb4b4b4}

Te6edf3_sf Tff7b72= Te6edf3sfTb4b4b4;

Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3setModulationParamsTb4b4b4(Te6edf3sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657long Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657int Te6edf3bw Tff7b72= Te6edf3_bwTb4b4b4;

Tff7b72switch Tb4b4b4(Te6edf3bwTb4b4b4) Tb4b4b4{

Tff7b72case T79c0ff0x00Tb4b4b4: Tff7b72return T79c0ff7.8E3Tb4b4b4;

Tff7b72case T79c0ff0x01Tb4b4b4: Tff7b72return T79c0ff15.6E3Tb4b4b4;

Tff7b72case T79c0ff0x02Tb4b4b4: Tff7b72return T79c0ff31.25E3Tb4b4b4;

Tff7b72case T79c0ff0x03Tb4b4b4: Tff7b72return T79c0ff62.5E3Tb4b4b4;

Tff7b72case T79c0ff0x04Tb4b4b4: Tff7b72return T79c0ff125E3Tb4b4b4;

Tff7b72case T79c0ff0x05Tb4b4b4: Tff7b72return T79c0ff250E3Tb4b4b4;

Tff7b72case T79c0ff0x06Tb4b4b4: Tff7b72return T79c0ff500E3Tb4b4b4;

Tff7b72case T79c0ff0x08Tb4b4b4: Tff7b72return T79c0ff10.4E3Tb4b4b4;

Tff7b72case T79c0ff0x09Tb4b4b4: Tff7b72return T79c0ff20.8E3Tb4b4b4;

Tff7b72case T79c0ff0x0ATb4b4b4: Tff7b72return T79c0ff41.7E3Tb4b4b4;

Tb4b4b4}

Tff7b72return T79c0ff0Tb4b4b4;

Tb4b4b4}

Tff7b72extern Tffa657bool Te6edf3lora_low_datarateTb4b4b4;

Tffa657void Td2a8ffsx126x::handleLowDataRateTb4b4b4(Tb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4( Tffa657longTb4b4b4( Tb4b4b4(T79c0ff1Tff7b72<Tff7b72<Te6edf3_sfTb4b4b4) Tff7b72/ Tb4b4b4(Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4)Tff7b72/T79c0ff1000Tb4b4b4)Tb4b4b4) Tff7b72> T79c0ff16Tb4b4b4)

Tb4b4b4{ Te6edf3_ldro Tff7b72= T79c0ff0x01Tb4b4b4; Te6edf3lora_low_datarate Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}

Tff7b72else Tb4b4b4{ Te6edf3_ldro Tff7b72= T79c0ff0x00Tb4b4b4; Te6edf3lora_low_datarate Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}

Tb4b4b4}

T8b949e// TODO: Check if there's anything the sx1262 can do here

Tffa657void Td2a8ffsx126x::optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4{ Tb4b4b4}

Tffa657void Td2a8ffsx126x::setSignalBandwidthTb4b4b4(Tffa657long Te6edf3sbwTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff7.8E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x00Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff10.4E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x08Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff15.6E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x01Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff20.8E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x09Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff31.25E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x02Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff41.7E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x0ATb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff62.5E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x03Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff125E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x04Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff250E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x05Tb4b4b4; Tb4b4b4}

Tff7b72else Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x06Tb4b4b4; Tb4b4b4}

Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;

Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;

Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Td2a8ffsx126x::setCodingRate4Tb4b4b4(Tffa657int Te6edf3denominatorTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{ Te6edf3denominator Tff7b72= T79c0ff5Tb4b4b4; Tb4b4b4}

Tff7b72else Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72> T79c0ff8Tb4b4b4) Tb4b4b4{ Te6edf3denominator Tff7b72= T79c0ff8Tb4b4b4; Tb4b4b4}

Tffa657int Te6edf3cr Tff7b72= Te6edf3denominator Tff7b72- T79c0ff4Tb4b4b4;

Te6edf3_cr Tff7b72= Te6edf3crTb4b4b4;

Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Td2a8ffsx126x::setPreambleLengthTb4b4b4(Tffa657long Te6edf3preamble_symbolsTb4b4b4) Tb4b4b4{

Te6edf3_preambleLength Tff7b72= Te6edf3preamble_symbolsTb4b4b4;

Te6edf3setPacketParamsTb4b4b4(Te6edf3preamble_symbolsTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Td2a8ffsx126x::setSyncWordTb4b4b4(Tffa657uint16_t Te6edf3swTb4b4b4) Tb4b4b4{

T8b949e// TODO: Why was this hardcoded instead of using the config value?

T8b949e// writeRegister(REG_SYNC_WORD_MSB_6X, (sw & 0xFF00) >> 8);

T8b949e// writeRegister(REG_SYNC_WORD_LSB_6X, sw & 0x00FF);

Te6edf3writeRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_MSB_6XTb4b4b4, T79c0ff0x14Tb4b4b4)Tb4b4b4;

Te6edf3writeRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_LSB_6XTb4b4b4, T79c0ff0x24Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Td2a8ffsx126x::setPinsTb4b4b4(Tffa657int Te6edf3ssTb4b4b4, Tffa657int Te6edf3resetTb4b4b4, Tffa657int Te6edf3dio0Tb4b4b4, Tffa657int Te6edf3busyTb4b4b4, Tffa657int Te6edf3rxenTb4b4b4) Tb4b4b4{

Te6edf3_ss Tff7b72= Te6edf3ssTb4b4b4;

Te6edf3_reset Tff7b72= Te6edf3resetTb4b4b4;

Te6edf3_dio0 Tff7b72= Te6edf3dio0Tb4b4b4;

Te6edf3_busy Tff7b72= Te6edf3busyTb4b4b4;

Te6edf3_rxen Tff7b72= Te6edf3rxenTb4b4b4;

Tb4b4b4}

Tffa657void Td2a8ffsx126x::dumpRegistersTb4b4b4(Te6edf3StreamTff7b72& Te6edf3outTb4b4b4) Tb4b4b4{

Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< T79c0ff128Tb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{

Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff0xTa5d6ff"Tb4b4b4)Tb4b4b4;

Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Te6edf3iTb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4;

Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff: 0xTa5d6ff"Tb4b4b4)Tb4b4b4;

Te6edf3outTb4b4b4.Te6edf3printlnTb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3iTb4b4b4)Tb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3ISR_VECT Td2a8ffsx126x::handleDio0RiseTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_PAYLOAD_CRC_ERROR_MASK_6XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{

Te6edf3_packetIndex Tff7b72= T79c0ff0Tb4b4b4;

Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; T8b949e// Read packet length

Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;

Tffa657int Te6edf3packetLength Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3_onReceiveTb4b4b4) Tb4b4b4{ Te6edf3_onReceiveTb4b4b4(Te6edf3packetLengthTb4b4b4)Tb4b4b4; Tb4b4b4}

Tb4b4b4}

Tffa657void Te6edf3ISR_VECT Td2a8ffsx126x::onDio0RiseTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3sx126x_modemTb4b4b4.Te6edf3handleDio0RiseTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657void Td2a8ffsx126x::setSPIFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{ Te6edf3_spiSettings Tff7b72= Te6edf3SPISettingsTb4b4b4(Te6edf3frequencyTb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657void Td2a8ffsx126x::enableCrcTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_crcMode Tff7b72= T79c0ff1Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657void Td2a8ffsx126x::disableCrcTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_crcMode Tff7b72= T79c0ff0Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657void Td2a8ffsx126x::explicitHeaderModeTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}

Tffa657void Td2a8ffsx126x::implicitHeaderModeTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_implicitHeaderMode Tff7b72= T79c0ff1Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3byte Td2a8ffsx126x::randomTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3readRegisterTb4b4b4(Te6edf3REG_RANDOM_GEN_6XTb4b4b4)Tb4b4b4; Tb4b4b4}

Te6edf3sx126x Te6edf3sx126x_modemTb4b4b4;

Tff7b72#Tff7b72endif

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